This invention relates generally to a method and apparatus for improving random pattern testing of logic structures, and more particularly to providing a test method and apparatus for random data testing of a logic structure in a functional manner.
Several existing test methods for random data testing of integrated circuits (ICs) are performed to detect defects or faulty circuit behavior, to thereby maintain proper functional operation of the ICs. One existing test method is a pseudo-random test method which is a built-in self test (BIST) including part of the internal circuitry in the IC and generating test patterns. The pseudo-random test method includes generating test patterns by initializing latches with random values and after a desired clock sequence, compressing the resulting latch values into a signature register or unloading the resulting latch values into observable registers or primary outputs (POs). In generating pseudo random patterns using the existing method, fault coverage is a typical metric utilized. The existing pseudo-random test method targets 100% fault coverage and some other existing methods have been employed which target less than 100% or n-detect where each detection is achieved via a different path. FIG. 1 shows a conventional configuration for random pattern testing. In FIG. 1, random data is generated by a random data source 1 and are shifted into multiple scan chains 2 using scan in (SI) ports. Test responses corresponding to the scan chains 2 are then collected in a signature register 4. FIGS. 2 and 3 are block diagrams illustrating a pre-disclosed method for enhancing random pattern test. Here, conventional scan chains are utilized for testing multiple registers and their downstream logic in a circuit under test.
FIG. 2 illustrates a conventional scan chain 10 having a master register 15 and a shadow register 20 located immediately downstream from the master register 15. In random data testing, randomly generated data bits from a pseudo-random pattern generator (not shown) are serially loaded into latches within the master register 15 and the shadow register 20. Data bits intended to be stored in the shadow register 20 first pass through the master register 15. Once the test data is generated and loaded into the registers 15 and 20, the data is used to test a logic circuit such as a comparator 25, for example. The comparator 25 compares each data bit in the master register 15 with a corresponding data bit in the shadow register 20. If the data bits match then the output 30 of the comparator will be equal to one. On the other hand, if the data bits do not match, then the output 30 is equal to zero. Further, a bitflip logic unit 50 and an associated weight logic 55 are provided for randomly inverting a bit sent through a parallel data path 40. The weight programmed into the weight logic 55 determines the likelihood of a given bit being flipped by the bitflip logic unit 50. Therefore, when it is desired to test the comparator 25 with a near match condition, a select mechanism 60 is activated to switch the source of the data to the shadow register 20 from the output data path 35 to the parallel data path 40, based on a value of an input control signal 45. The parallel data path 40 is routed through the bitflip logic unit 50, and the weight logic 55 is enabled. If no bit flipping is desired the bitflip logic unit 50 and the weight logic 55 are disabled and the data passes directly through the parallel data path 40 and into the shadow register 20. FIG. 3 illustrates conventional scan chains 100a and 100b having a master register 110 and multiple shadow registers 120a and 120b. Shadow registers 120a and 120b each have an associated select mechanism 140a and 140b and a bitflip logic unit including a weight logic 150a and 150b, respectively. The select mechanisms 140a and 140b are respectively activated to switch the source of the data to the shadow registers 140a and 140b, based on a value of input control signals 160a and 160b, respectively. A comparator 158 compares the data bits between the master register 110 and either the shadow register 120a or the shadow register 120b based upon a selection made by a select mechanism 155. There are several disadvantages associated with existing test methods, for example, linear dependencies occur with multiple registers being fed from a same random source when not in a special test mode. Another disadvantage is associated with the late mode timing paths of a circuit. Typically, the most critical late mode timing paths are difficult to test, and therefore a random test environment may not be implemented.
It would be desirable to be able to randomly test the logic structure in a functional manner. Further, it would be desirable to be able to modify a circuit configuration such that a critical late mode timing path will be more frequently tested during a pseudo-random test method.